A DAC such as a Capacitive DAC (CDAC) demands for a constant load impedance at its output over the instantaneous output bandwidth, i.e. the frequency range within which the output signal can be synthesized. Moreover, the load impedance presented to the DAC (e.g. a CDAC) should have a low value for optimum power transfer. For example, for a differentially implemented DAC, a full-scale single tone output power at the load may be calculated as follows:
                              P          OUT                =                              V            SUPPLY            2                                2            ·                          R              L                                                          (        1        )            
POUT denotes the maximum single-tone output power (obtained with a full-scale sine wave) that is delivered by the DAC to a load exhibiting an impedance RL. VSUPPLY denotes the supply voltage of the DAC.
For a more complex output signal of the DAC (e.g. a broadband signal characterized by a Peak-to-Average-Ratio, PAR, of more than two), the output power at the load may be calculated as follows:
                              P          OUT                =                              1                          PAR              2                                ·                                    V              SUPPLY              2                                      R              L                                                          (        2        )            
The PAR of DAC output signal x may be defined as follows:
                              PAR          ⁡                      (            x            )                          =                              x            PEAK                                x                          RM              ⁢                                                          ⁢              S                                                          (        3        )            
XPEAK denotes the maximum value of the DAC output signal x, whereas XRMS denotes the Root Mean Square (RMS) value of the DAC output signal x.
It can be seen from mathematical expressions (1) and (2) that the maximum DAC output power increases for decreasing load impedances RL coupled to the output of the DAC. Further, it can be seen that the load impedances should be lowered for a lower supply voltage in order to maintain a given output power level.
For example, a CDAC is inherently a pure AC DAC with a very low output impedance at Radio Frequency (RF) frequencies (when looking back from the load into the CDAC) since the series capacitors in the CDAC cells block DC currents. As described above in connection with mathematical expressions (1) and (2), the CDAC output power may be maximized by minimizing the load impedance directly connected to the CDAC. However, typically a predefined output impedance such as 100Ω (Ohm) is desired at the output of the CDAC in order to facilitate the interfacing with standard RF components (e.g. a filter, a mixer, a power amplifier or an antenna) of the transmit chain.
Hence, there may be a desire for an improved DAC architecture.